Low-Power CMOS Inverter with Enhancement-Mode Operation and Matched VTH at VDD=1 V on Monolayer 2D Material Channel

Efficient digital circuits require CMOS transistors with well-matched threshold voltage (VTH). In this work, we demonstrate for the first time CMOS co-integration, and well-matched VTH showcased through inverters based two-dimensional (2D) materials with supply voltage (VDD) of 1 V. We compare the fabrication of these circuits using the same channel material with using dedicated N and P channel materials (hetero-channel). Both instances use monolayer 2D transition metal dichalcogenide. The hetero-channel inverters allow superior performance at a relevant VDD=1 V: voltage gain exceeding 10 V/V, noise margin over 80%, low average static-power consumption ∼7 pW, and a switching voltage (VM)∼0.5 V. While still far from Si performance, reaching these numbers simultaneously requires multiple step developments working well together for monolayer 2D materials in the co-integrated flow. Sensitivity of various electrical metrics to process steps is also discussed in the paper.