Abstract
We present a fully cell-based All-Digital Phase-Locked Loop (ADPLL) with almost continuous tracking range of frequency. Using TSMC 0.18μm CMOS technology, this test chip can operate from 91.6MHz to 1.173GHz with an average resolution of 2.1ps. It features a new Mirror-DCO-Based Calibration Mechanism that enables smooth code-jumping to mitigate the segmented clock-period profile problem faced by most ADPLL's. This mechanism can suppress the jitter significantly when there is temperature and/or power supply variation during operation. This design has been validated in 0.18um CMOS technology. Measurement results show that when operating at 1GHz, the RMS jitter is 2.5ps and the peak-to-peak jitter is 15.3ps, respectively. © 2011 IEEE.