Abstract
This paper presents the design considerations of electrostatic discharge (ESD) protection for RF system-on-chip (SOC) in advanced CMOS technology. Different RF ESD protection strategies and circuit topologies are reviewed and discussed. The low-noise amplifiers (LNAs), often directly explored under the risk of ESD in wireless communication chips, are co-designed with the ESD blocks. By treating the ESD devices as a part of the input matching network, we demonstrate RF LNAs with excellent ESD protection, while the RF characteristics are almost unaffected. Using the proposed RF junction varactors for ESD design, a V-band LNA in 65 nm CMOS with a noise figure of 5.2 dB and a power gain of 10.9 dB presents a ESD protection level up to 4.0 KV, and also with the CDM ESD protection up to 8.7 A. ©2011 IEEE.