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Low-power testing for C-testable iterative logic arrays
Conference paper

Low-power testing for C-testable iterative logic arrays

Shih-Arn Hwang and Cheng-Wen Wu
International Symposium on VLSI Technology, Systems, and Applications, Proceedings, pp.355-358
1997

Abstract

Engineering (all)
Deterministic test patterns often lead to much larger power consumption than normal input patterns, resulting in higher tester requirement and testing cost. We show that, without affecting the test quality, the most power-efficient test set for C-testable iterative logic arrays can be obtained. The proposed method takes only polynomial time with respect to the cell size, and is independent of the array size.

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