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MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate
Conference paper   Peer reviewed

MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate

Yung-Hsien Wu, Lun-Lun Chen, Wei-Chia Chen, Chia-Chun Lin, Min-Lin Wu and Jia-Rong Wu
Microelectronic Engineering, Vol.88(7), pp.1361-1364
07/2011

Abstract

Ge-stabilized tetragonal ZrO2 High- gate dielectric NH3 plasma nitridation ZrO2/Ge/ZrO2 laminate
A Ge-stabilized tetragonal ZrO 2 (t-ZrO 2 ) film with permittivity (κ) of 36.2 was formed by depositing a ZrO 2 /Ge/ZrO 2 laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO 2 . On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO 2 gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. By passivating leaky channels derived from grain boundaries with NH 3 plasma, good leakage current of 4.8 × 10 -8 A/cm 2 at V g = V fb - 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained. © 2011 Elsevier B.V. All rights reserved.

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