Logo image
Back
Memory-Logic Hybrid Gate with 3D-Stackable Complementary Latches for FinFET-based Neural Networks
Conference paper

Memory-Logic Hybrid Gate with 3D-Stackable Complementary Latches for FinFET-based Neural Networks

Chieh Lee, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin and Ya-Chin King
Technical Digest - International Electron Devices Meeting, IEDM, Vol.2019-December, 8993511
12/2019
DOI: https://doi.org/10.1109/IEDM19573.2019.8993511
Appears in  keyword about Physics

Abstract

Electronic Optical and Magnetic Materials Condensed Matter Physics Electrical and Electronic Engineering Materials Chemistry
A memory-logic hybrid gate with complementary resistive switching pairs on vias in BEOL FinFET technologies with an area-efficient, 3D-stackable structures is proposed. Stable output logic stages enabled by the complementary states on the RRAM pair have been demonstrated. Through stacked-vias architectures, logic operations based on multiple non-volatile states are achieved.

Metrics

1 Record Views

Details

Logo image