Abstract
A traditional standard cell library consists of various functional cells with the same height, which could speed up VLSI design flow since designers could align cells to placement sites in rows. However, in advanced nodes, cells are designed with different heights. With mixed cell heights, we can design simple cells (e.g. inverters) as single-row-height cells, and complex cells (e.g. ip-ops) as multiple flow-height cells. Nevertheless, placement legalization becomes more dificult with mixed-cell-height libraries. In this paper, we propose a parallel legalization method for mixed-cell-height standard cell libraries to minimize total displacement. Experimental results show that our method has a 19% improvement on average in displacement compared with the state-of-the-art work [9].