Abstract
Controlling errors of critical dimension (CD) uniformity is crucial to achieving optimal IC performance, high chip yield and long lasting reliability. When the CDs to be resolved are less than the wavelength equipped by a lithographic exposure tool, the chip level CD variations caused by optical proximity effect (OPE) have been found significantly. With the relentlessly reduced CDs in integrated circuits the impact of OPE to chip yield and performance is much more profound and necessitates an inverse correction. In this paper, we report a model-based full-chip OPC on the contact hole layer of 0.13-μm logic circuits using 248-nm photo processing and attenuated phase-shifting mask (Att PSM). The final result demonstrates that OPE of random logic contact hole level can be greatly surpassed and controlled even with mask errors and their enhancement factors included of which are typically quite significant with layers of contact holes.