Modeling Step-and-Scan Overlay Error and Designing Sampling Strategies for Yield Improvement

Conference paper

Chen-Fu Chien, C. Hsu, W. Pan, Y. Wu and S. Lin

International Symposium on Semiconductor Manufacturing 2004 International Symposium on Semiconductor Manufacturing 2004, pp.455-459

2004

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Title: Modeling Step-and-Scan Overlay Error and Designing Sampling Strategies for Yield Improvement
Creators - without role: Chen-Fu Chien - 國立清華大學工學院工業工程與工程管理學系
C. Hsu
W. Pan
Y. Wu
S. Lin
Identifiers: 9957771386606774
Academic Unit: Department of Industrial Engineering and Engineering Management, College of Engineering, National Tsing Hua University
Language: Traditional Chinese
Resource Type: Conference paper
Publication Details: International Symposium on Semiconductor Manufacturing 2004 International Symposium on Semiconductor Manufacturing 2004, pp.455-459