Abstract
We address in this paper the defect modeling and testing of intra-cell bridging defects, from the layout perspective. For defect modeling, we incorporate a butterfly structure to resolve the potential non-logical effect a bridging defect may cause By doing so, a realistic Boolean fault model at the gate level can thus be generated for each defect under consideration. Furthermore, the test vectors can be generated by a formulation on top of existing ATPG tools. Experimental results indicate that simple stuck-at test set can only achieve 85% coverage for intra-cell bridging defects for, ISCAS85. The proposed systematic now can further boost it to 99%. ©2006 IEEE.