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Modular-addition signature analysis for built-in self-test
Conference paper

Modular-addition signature analysis for built-in self-test

Cheng-Wen Wu and Hun-Song Chen
IEEE Xplore Digital Library European Test Conference, 1993. Proceedings of ETC 93., Third, pp.457-465
1993

Abstract

Built-in self-test;Circuit faults;Circuit testing;Fault detection;Test pattern generators;Very large scale integration;Computational modeling;Circuit simulation;Hardware;Silicon Computer Science
The conventional multiple input signature register (MISR) has an average time to alias of 2/sup n/ (n is the length of the register), i.e., it aliasing probability is 1/2/sup n/. This paper presents a new cellular-automaton structure called modular-addition signature analyzer (MASA), which is shown to be an excellent alternative of MISR. It has a much lower hardware overhead than MISR based on equal aliasing probability. Experimental results show that, for n=16, MASA uses no more than 60% of the silicon area which MISR requires. The authors evaluate its ECs with respect to various error models, which shows consistently high ECs even for multiple errors. Its error coverages are easier to analyze than those of MISR. It can detect all single errors, multiple output stuck faults, and most of the unidirectional and bidirectional errors. In general, any error on a CUT output stream which makes the number of 1 s (modulo 4) being different from N (modulo 4) is detectable by MASA at a CUT output, where N is the correct number of 1 s at the CUT output stream

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