Abstract
This work proposes the rational Arnoldi method with adaplive orders for high-speed VLSI interconnect reductions. It is based on an extension of the classical multi-point Padé approximation by using the rational Arnoldi iteration approach. Given a set of expansion points, the transfer function error at each expansion point is derived first. In each iteration of the propose algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. The corresponding reduced-order model yields the greatest output moment improvement. © 2004 IEEE.