Abstract
Floorplanning is a crucial process in the early stage of VLSI physical design. It determines the performance, reliability, and size of chips. B∗-tree is a simple yet efficient representation that encodes the layout of modules in a compact and non-slicing structure. Several B∗-tree variants and corresponding operators have been proposed to deal with non-slicing floorplanning. However, these operators are considered and applied individually. A collective manipulation of them remains missing. This study proposes a genetic algorithm (GA) that enables multiple crossover and mutation operators for solving the non-slicing floorplanning problem. In particular, the GA selects one crossover operator and one mutation operator from the pool of operators whenever reproducing an offspring. The probability for an operator to be selected is based on its empirical performance. This study conducts experiments on two well-known benchmarks to examine the effectiveness of the proposed method. The experimental results show that the GA can achieve superior solution quality and efficiency on the non-slicing VLSI floorplanning.