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Multiple Delayed Signal Cancellation Filter-Based Enhanced Frequency-Locked Loop under Adverse Grid Conditions
Conference paper

Multiple Delayed Signal Cancellation Filter-Based Enhanced Frequency-Locked Loop under Adverse Grid Conditions

Surya Chandra Gulipalli, Srinivas Gude and Chia-Chi Chu
Conference Record - IAS Annual Meeting (IEEE Industry Applications Society), Vol.2021-October
2021

Abstract

Filters Frequency-locked loop (FLL) Phase-locked loop (PLL) Power system harmonics Synchronization Control and Systems Engineering Industrial and Manufacturing Engineering Electrical and Electronic Engineering
Accurate and prompt estimation of phase angles, frequency, and magnitudes of the grid voltage is extremely important in paving a good platform for a fast and reliable operation of grid monitoring, protection, and control. The phase-locked loop (PLL) served this purpose for decades. However, a major concern of the PLL is its bandwidth and disturbance rejection capabilities that trade with the speed of parameters detection in inverse proportion. To overcome this difficulty, the concept of the Frequency-locked loop (FLL) has been proposed recently. Even though FLL and PLL share some similarities, some differences still exist, especially in their in-loop filtering capability. To this end, the multiple delayed signal cancellation (MDSC) filter is considered at the in-loop stage of the FLL for enriching FLL's performance. This paper focuses on applying αβ-frame MDSC filters and compares its effectiveness with various filtering techniques. Experimental studies in real-time digital simulations demonstrate that the performance of the proposed MDSC-based FLL is appreciable even under adverse grid conditions.

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