Abstract
This paper presents a parallel vector simulation-based approach to locating multiple errors in large combinational circuits. Two heuristics are proposed to avoid the explosion of the error space. Experimental results on a set of ISCAS'85 and two large benchmarks show that our approach efficiently identifies a small set of correctable nodes that contains the actual error sources. Thus, further error correction can be conducted on the erroneous implementation. ©2008 IEEE.