Abstract
As the deep convolutional neural network (DCNN) has achieved success in many artificial intelligence areas, most of the major commercial and academic research Institutes continue renewing the architecture of deep learning hardware accelerators to meet the requirements for high performance, low power and adaptability to various neural networks. Since the affordable on-chip storage cannot accommodate the whole data of even a convolutional layer in modern DCNNs, the computation process of a convolutional layer has to be partitioned into multiple pieces and then scheduled to processing elements on accelerators. This workload scheduling is required to be considered simultaneously with hardware architecture, and the design and configuration parameters are so complicated that design exploration can be difficult in traditional register-transfer level. In this paper, we propose a virtual platform for DCNN accelerator design. Compared to RTL implementation, the proposed model has a worst-case error of 97-99%, with 3000-13000 x simulation speedup.