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NVM Duet: Unified working memory and persistent store architecture
Conference paper

NVM Duet: Unified working memory and persistent store architecture

Ren-Shuo Liu, De-Yu Shen, Chia-Lin Yang, Shun-Chih Yu and Cheng-Yuan Michael Wang
International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS, pp.455-469
2014

Abstract

Consistency Durability Memory management Memory scheduler Non-volatile memory Phase-change memory Refresh Resistance distribution Resistance drift Storage-class memory
Emerging non-volatile memory (NVM) technologies have gained a lot of attention recently. The byte-addressability and high density of NVM enable computer architects to build large-scale main memory systems. NVM has also been shown to be a promising alternative to conventional persistent store. With NVM, programmers can persistently retain in-memory data structures without writing them to disk. Therefore, one can envision that in the future, NVM will play the role of both working memory and persistent store at the same time. Persistent store demands consistency and durability guarantees, thereby imposing new design constraints on the memory system. Consistency is achieved at the expense of serializing multiple write operations. Durability requires memory cells to guarantee non-volatility and thus reduces the write speed. Therefore, a unified architecture oblivious to these two use cases would lead to suboptimal design. In this paper, we propose a novel unified working memory and persistent store architecture, NVM Duet, which provides the required consistency and durability guarantees for persistent store while relaxing these constraints if accesses to NVM are for working memory. A cross-layer design approach is adopted to achieve the design goal. Overall, simulation results demonstrate that NVM Duet achieves up to 1:68× (1:32× on average) speedup compared with the baseline design. Copyright is held by the owner/author(s).

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