Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION

C.-J. Su; Y.-T. Tang; Y.-C. Tsou; P.-J. Sung; F.-J. Hou; C.-J. Wang; S.-T. Chung; C.-Y. Hsieh; Y.-S. Yeh; F.-K. Hsueh; K.-H. Kao; S.-S. Chuang; C.-T. Wu; T.-Y. You; Y.-L. Jian; T.-H. Chou; Y.-L. Shen; B.-Y. Chen; G.-L. Luo; T.-C. Hong; K.-P. Huang; M.-C. Chen; Y.-J. Lee; T.-S. Chao; T.-Y. Tseng; W.-F. Wu; G.-W. Huang; J.-M. Shieh; W.-K. Yeh; Y.-H. Wang

doi:10.23919/VLSIT.2017.7998159

Conference paper

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION

C.-J. Su, Y.-T. Tang, Y.-C. Tsou, P.-J. Sung, F.-J. Hou, C.-J. Wang, S.-T. Chung, C.-Y. Hsieh, Y.-S. Yeh, F.-K. Hsueh, …

Digest of Technical Papers - Symposium on VLSI Technology, pp.T152-T153

07/2017

DOI: https://doi.org/10.23919/VLSIT.2017.7998159

Abstract

Electrical and Electronic Engineering

Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrO x (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al 2 O 3 IL results in paraelectric behavior, HZO on GeO x IL exhibits significant FE. High I on /I off (> 107) and low subthreshold slope (S.S. ∼ 58 mV/dec.) are demonstrated by a Ge nFinFET with a gate length (L g ) of 60 nm and a FE-HZO/GeO x gate stack.

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Title: Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION
Translated title: Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION
Creators - without role: C.-J. Su - National Institutes of Applied Research
Y.-T. Tang - National Institutes of Applied Research
Y.-C. Tsou - National Cheng Kung University
P.-J. Sung - National Institutes of Applied Research
F.-J. Hou - National Institutes of Applied Research
C.-J. Wang - National Institutes of Applied Research
S.-T. Chung - National Yang Ming Chiao Tung University
C.-Y. Hsieh - National Sun Yat-sen University
Y.-S. Yeh - National Institutes of Applied Research
F.-K. Hsueh - National Yang Ming Chiao Tung University
K.-H. Kao - National Cheng Kung University
S.-S. Chuang - National Yang Ming Chiao Tung University
C.-T. Wu - National Institutes of Applied Research
T.-Y. You - National Institutes of Applied Research
Y.-L. Jian - National Institutes of Applied Research
T.-H. Chou - National Institutes of Applied Research
Y.-L. Shen - National Institutes of Applied Research
B.-Y. Chen - National Institutes of Applied Research
G.-L. Luo - National Institutes of Applied Research
T.-C. Hong - National Cheng Kung University
K.-P. Huang - Industrial Technology Research Institute
M.-C. Chen - National Institutes of Applied Research
Y.-J. Lee - National Institutes of Applied Research
T.-S. Chao - National Yang Ming Chiao Tung University
T.-Y. Tseng - National Yang Ming Chiao Tung University
W.-F. Wu - National Institutes of Applied Research
G.-W. Huang - National Institutes of Applied Research
J.-M. Shieh - National Institutes of Applied Research
W.-K. Yeh - National Institutes of Applied Research
Y.-H. Wang - National Institutes of Applied Research
Publication Details: Digest of Technical Papers - Symposium on VLSI Technology, pp.T152-T153
Identifiers: 9784863486058; 9957775465406774
Academic Unit: Department of Engineering and System Science, College of Nuclear Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION

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