Abstract
Recently studies have shown that by adapting high-K gate dielectric, deep sub-micron MOSFET suffers short channel effect caused by the fringing electric fields from gate to source/drain regions. In this work, a simulation-based analysis of multiple gate stack structure with channel length as low as 50nm is presented. The new stake gate structure can be optimized for reducing the undesirable fringing induced barrier lowing effect of in a high-K gate dielectric device.