Abstract
This paper presents a novel systolic array with log 2 N multipliers and 3log 2 N adders for computing the N-point discrete Hartley transform, where N is a power of two. The architecture reaches a throughput of one complete N-point transform per N clock cycles, i.e., one transform sample per clock cycle. It possesses the features of regularity and modularity, and is thus well suited to VLSI implementation. As compared to existing related systolic/regular designs, the proposed one gains improvements in area-time complexity.