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Novel wafer level packaging for large die size device
Conference paper

Novel wafer level packaging for large die size device

T.N. Chang, C.Y. Tsou, B.H. Wang and K.N. Chiang
2017 International Conference on Electronics Packaging, ICEP 2017, pp.292-296
06/2017

Abstract

FEM simulation Optical device Packaging ShellCase WLCSP Electrical and Electronic Engineering Industrial and Manufacturing Engineering Electronic Optical and Magnetic Materials
As the demand for higher resolution electronic device grows, manufacturers are seeking ways to put as much as possible pixels with using less and less space. Compare with land grid array (LGA) type packaging, WLCSP technology provide a way to shrink the package size. ShellCase WLCSP is one of the types with good reliability and small packaging size used in image sensor. But the double side glass structure might have reliability problem while building with large die size. Means the number of pixel will be constrained by chip size. A new optical packaging patent for CMOS image sensors is discussed in this paper. This package is a chip on glass fan-out structure. Compare with ShellCase Wafer Level Chip Scale Packaging (WLCSP) the glass on print circuit board (PCB) side is removed. Therefore, larger die size can be used in this packaging. In this paper, the thermal cycling test (TCT) reliability for fan-out packaging is discussed through finite element method (FEM).

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