Logo image
On Stockmeyer's Floorplan Optimizatioin Technique
Conference paper

On Stockmeyer's Floorplan Optimizatioin Technique

T.-C. Wang and D. F. Wong
IEEE Xplore Digital Library IEEE International Symposium on Circuits and Systems (ISCAS), Vol.4, pp.1989-1992
1992

Abstract

circuit layout;computational complexity;network topology

Studies the time complexity of L. Stockmeyer's technique (1993) to solve the floorplan area optimization problem for hierarchical floorplans of order 5. The authors develop a method of constructing bad floorplans to show that Stockmeyer's technique inherently has exponential time complexity. The special case is considered where the modules all have integer dimensions, and it is shown that this problem can be solved in pseudopolynomial time by Stockmeyer's technique. For the general case in which the dimensions are real numbers, a pseudopolynomial-time ε-approximation algorithm is presented for solving this problem. The last two results can also be extended to hierarchical floorplans of higher order

Metrics

1 Record Views

Details

Logo image