On-chip TSV testing for 3D IC before bonding using sense amplification

Po-Yuan Chen; Cheng-Wen Wu; Ding-Ming Kwai

doi:10.1109/ATS.2009.42

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Conference paper

On-chip TSV testing for 3D IC before bonding using sense amplification

Po-Yuan Chen, Cheng-Wen Wu and Ding-Ming Kwai

Proceedings of the Asian Test Symposium, pp.450-455

2009

DOI: https://doi.org/10.1109/ATS.2009.42

Abstract

3D IC

Defect-based testing

Interconnection test

Sense amplifier

TSV

Electrical and Electronic Engineering

We present a novel testing scheme for TSVs in a 3D IC by performing on-chip TSV monitoring before bonding, using a sense amplification technique that is commonly seen on a DRAM. By virtue of the inherent capacitive characteristics, we can detect the faulty TSVs with little area overhead for the circuit under test. © 2009 IEEE.

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Title: On-chip TSV testing for 3D IC before bonding using sense amplification
Translated title: On-chip TSV testing for 3D IC before bonding using sense amplification
Creators - without role: Po-Yuan Chen - Department of Electrical Engineering , National Tsing Hua University
Cheng-Wen Wu - Department of Electrical Engineering , National Tsing Hua University
Ding-Ming Kwai - Industrial Technology Research Institute
Publication Details: Proceedings of the Asian Test Symposium, pp.450-455
Identifiers: 9780769538648; 9957770384906774
Academic Unit: College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

On-chip TSV testing for 3D IC before bonding using sense amplification

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