On-chip contrastive divergence learning in analogue VLSI

Patrice Fleury; Hsin Chen; Alan F. Murray

doi:10.1109/IJCNN.2004.1380863

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Conference paper

On-chip contrastive divergence learning in analogue VLSI

Patrice Fleury, Hsin Chen and Alan F. Murray

IEEE International Conference on Neural Networks - Conference Proceedings, Vol.3, pp.1723-1728

2004

DOI: https://doi.org/10.1109/IJCNN.2004.1380863

Abstract

We have mapped the contrastive divergence learning scheme of the Product of Experts (PoE) onto electrical circuits. The issues raised during that hardware translation are discussed in this paper and some circuits presenting our solutions described. The entire learning rule is implemented in mixed-signal VSLI on a 0.6μm CMOS process. Chips results validating our approach and methodology are also presented.

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Title: On-chip contrastive divergence learning in analogue VLSI
Creators - without role: Patrice Fleury - National Microelectronics Institute
Hsin Chen - National Microelectronics Institute
Alan F. Murray - National Microelectronics Institute
Publication Details: IEEE International Conference on Neural Networks - Conference Proceedings, Vol.3, pp.1723-1728
Grant note: IEEE Neural Networks Society, INNS
Identifiers: 0780383591; 9957769359806774
Academic Unit: Institute of Electronics Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

On-chip contrastive divergence learning in analogue VLSI

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