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On fault-tolerant FFT butterfly network design
Conference paper

On fault-tolerant FFT butterfly network design

Shyue-Kung Lu, Cheng-Wen Wu and Sy-Yen Kuo
Proceedings - IEEE International Symposium on Circuits and Systems, Vol.2, pp.69-72
1996

Abstract

Electrical and Electronic Engineering Electronic Optical and Magnetic Materials
We present novel fault-tolerant methods for FFT processors. A reconfiguration mechanism is used to bypass the faulty cell. Special cell designs are presented which implement the reconfiguration algorithm. The reliability of the FFT system increases significantly, with about 16% and 25% hardware overhead for the bit-level and module-level designs, respectively.

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