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On-line error detection schemes for a systolic finite-field inverter
Conference paper

On-line error detection schemes for a systolic finite-field inverter

Yu-Chun Chuang and Cheng-Wen Wu
Proceedings of the Asian Test Symposium, pp.301-305
1998

Abstract

Electrical and Electronic Engineering
Galois-field (GF) is a number system with a finite set of elements. It is widely used in error-control coding, cryptography, etc. Among its important arithmetic operations, inversion and division have been identified as the most complicated. In this paper, concurrent error detection (CED) schemes have been presented for a systolic GF(2 m ) inverter that we have proposed recently. The CED circuitry tests the inverter concurrently while it is in normal operation to increase the reliability of the inverter. There is negligible performance penalty. Analysis shows that all single cell faults can be detected concurrently. The area overhead is less than 5% for 11 bits or longer words.

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