On the design of a fault-tolerant systolic array multiplier using time redundancy

Conference paper

T.-Y. Chang, C.-W. Wu, C.-C. Wang and J.-B. Shu

Proc. Int. Symp. on IC Design and Manufacturing (ISIC), pp.497-502

1991

Abstract

systolic;multiplier;redundancy

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Title: On the design of a fault-tolerant systolic array multiplier using time redundancy
Creators - without role: T.-Y. Chang
C.-W. Wu - 國立清華大學電機資訊學院電機工程學系
C.-C. Wang
J.-B. Shu
Publication Details: Proc. Int. Symp. on IC Design and Manufacturing (ISIC), pp.497-502
Identifiers: 9957774509806774
Academic Unit: College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: Traditional Chinese
Resource Type: Conference paper