Abstract
Adiabatic quantum-flux parametron (AQFP) is a superconducting technology with extremely low power consumption compared to traditional CMOS structure. Since AQFP logic gates are all clocked by AC current, extra buffer cells are required for balancing the length of data paths. Furthermore, since the output current of an AQFP logic gate is too weak to drive more than one gate, splitter cells are needed for branching the output signals of multi-fanout gates. For an AQFP circuit, the total number of additional buffers and splitters may be much more than the number of logic gates (up to 9 times in the benchmark circuits after optimization), which would greatly impact the power, performance, and area of the circuit. In this paper, we propose several techniques to (i) reduce the total number of required buffers and splitters, and (ii) perturb the levels of logic gates in order to seek more optimization opportunities for buffer and splitter reduction. Experimental results shows that our approach has better quality with comparable runtime compared to a retiming-based method from ASP-DAC'23. Moreover, our approach has quality which is on equal footing with the integer linear programming-based method also from ASP-DAC'23.