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Optimization of AI SoC with Compiler-Assisted Virtual Design Platform
Conference paper

Optimization of AI SoC with Compiler-Assisted Virtual Design Platform

Chih-Tsun Huang, Juin-Ming Lu, Yao-Hua Chen, Ming-Chih Tung and Shih-Chieh Chang
Proceedings of the International Symposium on Physical Design, pp.187-193
03/2023

Abstract

AI compiler Deep neural networks Electronic system-level ESL Hardware accelerator System-on-chip Virtual platform Electrical and Electronic Engineering
As deep learning keeps evolving dramatically with rapidly increasing complexity, the demand for efficient hardware accelerators has become vital. However, the lack of software/hardware co-development toolchains makes designing AI SoCs (artificial intelligent system-on-chips) considerably challenging. This paper presents a compiler-Assisted virtual platform to facilitate the development of AI SoCs from the early design stage. The electronic system-level design platform provides rapid functional verification and performance/energy analysis. Cooperating with the neural network compiler, AI software and hardware can be co-optimized on the proposed virtual design platform. Our Deep Inference Processor is also utilized on the virtual design platform to demonstrate the effectiveness of the architectural evaluation and exploration methodology.

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