P-channel Schottky barrier nanowire SONOS memory with low-voltage operations and excellent reliability

Wei Chang; Chun-Hsing Shih; Wen-Fa Wu; Chenhsin Lien

doi:10.1109/VLSI-TSA.2012.6210104

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Conference paper

P-channel Schottky barrier nanowire SONOS memory with low-voltage operations and excellent reliability

Wei Chang, Chun-Hsing Shih, Wen-Fa Wu, Wen-Fa Wu and Chenhsin Lien

International Symposium on VLSI Technology, Systems, and Applications, Proceedings, 6210104

2012

DOI: https://doi.org/10.1109/VLSI-TSA.2012.6210104

Abstract

An ultralow voltage p-channel Schottky barrier nanowire SONOS memory is reported experimentally with excellent reliability. By applying pure metallic Schottky barrier S/D, the nanowire SONOS memory can operate at a gate voltage of -7V to -11V for hole programming, and 5V to 7V for electron erasing. This Schottky barrier cell exhibits superior 10K cycling and 125°C retention for practical applications. © 2012 IEEE.

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Title: P-channel Schottky barrier nanowire SONOS memory with low-voltage operations and excellent reliability
Creators - without role: Wei Chang - National Tsing Hua University
Chun-Hsing Shih - National Chi Nan University
Wen-Fa Wu - National Institutes of Applied Research
Wen-Fa Wu - National Institutes of Applied Research
Chenhsin Lien - National Tsing Hua University
Publication Details: International Symposium on VLSI Technology, Systems, and Applications, Proceedings, 6210104
Identifiers: 9781457720840; 9957771542206774
Academic Unit: College of Electrical Engineering and Computer Science, National Tsing Hua University; Department of Engineering and System Science, College of Nuclear Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

P-channel Schottky barrier nanowire SONOS memory with low-voltage operations and excellent reliability

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