Partitioning Combinational Circuits in Graph and Logic Domains

Conference paper

D.I. Cheng, S.C. Chang and M. Marek-Sadowska

Workshop on Synthesis and Systems Integration of Mixed Information Technologies, Vol.93, pp.404-6

1993

Abstract

Partitioning Combinational Circuits;Graph;Logic Domains

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Title: Partitioning Combinational Circuits in Graph and Logic Domains
Creators - without role: D.I. Cheng
S.C. Chang - 國立清華大學電機資訊學院資訊工程學系
M. Marek-Sadowska
Identifiers: 9957774687206774
Academic Unit: Department of Computer Science, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: Traditional Chinese
Resource Type: Conference paper
Publication Details: Workshop on Synthesis and Systems Integration of Mixed Information Technologies, Vol.93, pp.404-6