The hybrid poly-Si fin channel junctionless (JL) field-effect transistors (FET) are fabricated first. This novel devices show stable temperature/reliability characteristics, and excellent electrical performances in terms of a steep SS (64mV/dec), a high I-on/I-off current ratio (>10(7)) and a small DIBL (3mV/V) by reducing the effective channel thickness that is caused by the hybrid P+ channel and n-type substrate (hybrid P/N) junction. In addition, the novel P/N JL-TFT shows smaller series resistance and less current crowding than convectional JL-TFT with ultra-thin channel. Furthermore, our device can be supported by simulated results using technology computer-aided design (TCAD) simulation. Hence, the proposed hybrid P/N JL-TFTs are highly promising for future further scaling.
- Performance Enhancement of a Novel P-type Junctionless Transistor Using a Hybrid Poly-Si Fin Channel
- Ya-Chi Cheng - Natl Tsing Hua Univ, Dept Engn & Syst Sci, Hsinchu 30013, TaiwanHung-Bin Chen - Natl Tsing Hua Univ, Dept Engn & Syst Sci, Hsinchu 30013, TaiwanChi-Shen Shao - Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 30050, TaiwanJun-Ji Su - Natl Tsing Hua Univ, Dept Engn & Syst Sci, Hsinchu 30013, TaiwanYung-Chun Wu - Natl Tsing Hua Univ, Dept Engn & Syst Sci, Hsinchu 30013, TaiwanChun-Yen Chang - Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 30050, TaiwanTing-Chang Chang - Sun Yat-sen UniversityIEEE
- IEEE International Electron Devices Meeting
- IEEE
- 4
- Conference paper
- 01/01/2014
- 2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
- English