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Performance Step-Up in PMOS with Monolayer WSe2 Channel
Conference paper

Performance Step-Up in PMOS with Monolayer WSe2 Channel

Ang-Sheng Chou, Yu-Tung Lin, Ming-Yang Li, Po-Sen Mao, Ching-Hao Hsu, Sui-An Chou, Yu-Wei Hsu, Shuer Ku, Goutham Arutchelvan, Wei-Sheng Yun, …
2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
06/2025

Abstract

Performance evaluation;Surface resistance;Tungsten;Voltage;Doping;Logic gates;Very large scale integration;Contact resistance;Hysteresis

This study makes monolayer (1L) tungsten diselenide (WSe2) more competitive as a scaled p-channel candidate. We address performance constraints related to channel, dielectric, and contact while reducing device-to-device variability. Back-gated PMOS with 1L-WSe2 channel and effective oxide thickness (EOT) of 1.2 nm reaches ON-current of 400 µA/µm at VDS of -1 V, with subthreshold swing of 72 mV /decade, ON/OFF ratio of 7 orders, nearly hysteresis-free, while operating in enhancement-mode. Furthermore, passivation allowing for air stability is implemented without performance degradation. This is achieved without the use of materials that are not compatible with wet processing. We identify contact resistance and specifically the need for gate-voltage-independent contact resistance as the main next step for improving device performance.

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