Abstract
Significant advances in VLSI process technology have scaled 'the feature size down. One effect of this scaling down is that coupling capacitances have grown reciprocal in the square of the scaling factor. This crosstalk effect will not only increase the power consumption but also lengthen the propagation delay. Since the data sequences on an instruction bus are known during, the compile time, this paper presents two post-compiler algorithms, rescheduling and renaming, for performance improvement by eliminating crosstalk effects on an instruction bus. The results show that our crosstalk-eliminating postcomplier algorithms significantly reduce the dynamic instruction overhead from 11.50% to 0.52% by eliminating the 4·C crosstalk. Due to the effective 4·C crosstalk elimination, our proposed method can improve the instruction fetch time up to 9.59%. © 2006 IEEE.