Abstract
In this paper, we present a performance-driven soft-macro clustering and placement method which preserves HDL design hierarchy to guide the soft-macro placement process. We also present a complete chip design methodology by integrating the proposed method and a set of commercial EDA tools. Experiments on three industrial designs ranging from 75 K to 230 K gates demonstrate that the proposed soft-macro clustering and placement method improves critical-path delay on an average of 24%.