Abstract
This paper presents a novel technique for extracting fundamental frequency positive sequence (FFPS) component of the grid voltage based on multiple delayed signal cancellation (MDSC). This technique can be used as a pre-filter of conventional phase-locked loop (PLL) for grid synchronization. With this the dynamic performance of the PLL is enhanced even under disturbed grid voltage conditions. In comparison with classical generalized delayed signal cancellation (GDSC) and cascaded delayed signal cancellation (CDSC) techniques, the new MDSC technique provides more flexibility to configure the undesired order of harmonics, improved response time and requires less memory for delay blocks. To further improve the response time of the method, variable time-period MDSC (VT-MDSC) is also proposed. Both qualitative analysis and numerical experiments have been performed to demonstrate advantages of the proposed techniques.