Abstract
A junctionless (JL) gate-all-around (GAA) nanosheet polycrystalline silicon (poly-Si) 2nm channel thin-film transistor (TFT) has been successfully demonstrated. The sub-threshold swing (SS) of 61 mV/decade has been the record reported to date in JL TFTs, and the I on /I off current ratio is 10 8 . The cumulative distribution in nanosheet 2-nm channel is small. JL-GAA TFTs show a low drain-induced barrier lowering (DIBL) value of 6 mV/V for L G =60nm, excellent gate control and reduced sensitivity to temperature in terms of V TH and SS. The JL-GAA TFTs of good device characteristics along with simple fabrication are highly promising for future (system-on-panel) SOP and system-on-chip (SOC) applications. © 2013 JSAP.