Logo image
Phase noise analysis of an integrated voltage-controlled oscillator with a novel graphical optimization method
Conference paper

Phase noise analysis of an integrated voltage-controlled oscillator with a novel graphical optimization method

Ming-Chun Su, Chia-Wei Wu and Klaus Yung-Jane Hsu
2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings, pp.189-192
2002

Abstract

A novel three-dimensional phase noise analysis diagram is presented. The minimization of phase noise and obtaining optimum bias condition through this process become more systematic and accurate. This visualization methodology increases design efficiency. Furthermore, a 2.4GHz fully integrated LC voltage-controlled oscillator (VCO) in a 0.25μm CMOS technology was designed using this optimization method. The resultant phase noise is -123 dBc/Hz at 1MHz offset from a 2.44GHz carrier. The designed VCO dissipates 3mA from a 1.5V supply voltage.

Metrics

1 Record Views

Details

Logo image