Abstract
In modern SOC design, a large number of buffers need to be inserted to a large number of nets to improve performance and/or signal integrity. These buffers increase the power consumption and occupy silicon area. So it is important to avoid over-buffering. Buffering spaces are more limited in the denser regions of a layout. Thus it is also necessary to reserve the more premium buffering spaces in the denser regions until they are absolutely needed during physical synthesis. This paper presents a buffer insertion algorithm with consideration of both power dissipation and design density under a given timing constraint. We propose a formulation for this multiobjective problem and a heuristic solver using Lagrangian relaxation technique. Experiment shows that our method can significantly improve the overall design density while achieving low power. ©2008 IEEE.