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Processor SER Estimation with ACE Bit Analysis
會議論文

Processor SER Estimation with ACE Bit Analysis

Ting-Shuo Hsu, Dun-an Yang, Wang Liao, Masatoshi Itoh, Masanori Hashimoto 和 Jing-Jia Liou
2021 21th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 頁碼.1-5
IEEE
2021 21th European Conference on Radiation and Its Effects on Components and Systems (RADECS) (Vienna, Austria, 13/09/2021–17/09/2021)
09/2021
DOI: https://doi.org/10.1109/RADECS53308.2021.9954474
Web of Science ID: WOS:000904311100024

摘要

ACE Error analysis Estimation Irradiation Test Multicore processing Processor Program processors Random access memory RISC-V SER Europe Radiation Effects
Estimating the soft error rate (SER) for processors is imperative to adopt a proper hardening technique for increasing the system reliability. Aiming to estimate the functional error rates, we propose to scale the baseline SER estimated with physical memory sizes by the fraction of architecturally correct execution (ACE) bits of memory elements (SRAM, caches and registers). We compared the scaled SER with the measured SER under neutron irradiation for a multi-core processor and confirmed a good consistency.

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