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Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs
Conference paper

Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs

Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh and Cheng-Wen Wu
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp.429-434
2013
DOI: https://doi.org/10.1109/ASPDAC.2013.6509634

Abstract

Computer Science Applications Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering
With the rapid popularization of mobile devices, the low-power and energy-efficient became far more important than the system operating frequency. This work demonstrates a processor and DRAM integration scheme by TSV-based 3-D stacking and the performance and energy efficiency is evaluated by an ESL design methodology. The integration scheme comprising Sans-Cache DRAM (SCDRAM) architecture which is designed under the power and energy considerations is explored. Experiment results show the proposed architecture can greatly reduce 80% energy while having 23.5% of system performance improvement. © 2013 IEEE.

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