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Processor-programmable memory BIST for bus-connected embedded memories
Conference paper

Processor-programmable memory BIST for bus-connected embedded memories

Ching-Hong Tsai and Cheng-Wen Wu
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Vol.2001-January, pp.325-330
2001

Abstract

Assembly Automatic testing Built-in self-test Circuit testing Microprocessors Random access memory Signal generators System testing System-on-a-chip Test pattern generators Electrical and Electronic Engineering Computer Science Applications Computer Graphics and Computer-Aided Design
We present a processor-programmable built-in self-test (BIST) scheme suitable for embedded memory testing in the system-on-a-chip (SOC) environment. The proposed BIST circuit can be programmed via an on chip microprocessor. Upon receiving the commands from the microprocessor, the BIST circuit generates pre-defined test patterns and compares the memory outputs with the expected outputs. Most popular memory test algorithms can be realized by properly programming the BIST circuit using the processor instructions. Compared with processor-based memory BIST schemes that use an assembly-language program to generate test patterns and compare the memory outputs, the test time of the proposed memory BIST scheme is greatly reduced.

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