Abstract
Program/erase characteristics of twin Poly-Si Thin Film Transistors (TFTs) EEPROM utilizing tri-gate nanowires (NWs) was demonstrated. The NWs TFT has superior gate control due to its tri-gate structure leads to higher memory window and efficiency than single-channel (SC) one. The device different gate lengths characteristics and reliability were also addressed. The capacitance ratio of proposed device of 4:1 shows optimum value in P/E operation. The present work illustrates the possibility for future system-on-panel (SOP) and 3D Flash memory application.