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RAMSES: A fast memory fault simulator
Conference paper

RAMSES: A fast memory fault simulator

Chi-Feng Wu, Chih-Tsun Huang and Cheng-Wen Wu
Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999, pp.165-173
1999

Abstract

Hardware and Architecture Electrical and Electronic Engineering Safety Risk Reliability and Quality
In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some well-known memory fault models, the algorithm that we developed ensures that new fault models can be included easily by adding new fault descriptors instead of modifying the algorithm or program. With RAMSES, the time complexity of memory fault simulation is improved from O(N 3 ) to O(N 2 ), where N is the memory capacity in terns of bits. Our approach requires only a small amount of extra memory space. Simulation results by RAMSES show that running the proposed cocktail-March tests can significantly reduce the test time. With the help of RAMSES, an efficient test algorithm called March-CW was developed for word-oriented memories.

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