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RSA cryptosystem design based on the Chinese remainder theorem
Conference paper

RSA cryptosystem design based on the Chinese remainder theorem

Chung-Hsien Wu, Jin-Hua Hong and Cheng-Wen Wu
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Vol.2001-January, pp.391-395
2001
DOI: https://doi.org/10.1109/ASPDAC.2001.913338

Abstract

Algorithm design and analysis Cathode ray tubes Clocks CMOS technology Communications technology Cryptography Delay Hardware Systolic arrays Throughput Computer Science Applications Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering
In this paper, we present the design and implementation of a systolic RSA cryptosystem based on a modified Montgomery's algorithm and the Chinese Remainder Theorem (CRT) technique. The CRT technique improves the throughput rate up to 4 times in the best case. The processing unit of the systolic array has 100% utilization because of the proposed block interleaving technique for multiplication and square operations in the modular exponentiation algorithm. For 512-bit inputs, the number of clock cycles needed for a modular exponentiation is about 0.13M to 0.24M. The critical path delay is 6.13 ns using a 0.6 μm CMOS technology. With a 150 MHz clock, we can achieve an encryption/decryption rate of about 328 to 578 Kb/s.

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