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Realization and optimization of H.264 decoder for dual-core SOC
Conference paper

Realization and optimization of H.264 decoder for dual-core SOC

Jia-Ming Chen, Chiu-Ling Chen, Jian-Liang Luo, Po-Wen Cheng, Chia-Hao Yu, Shau-Yin Tseng and Wei-Kuan Shih
SIGMAP 2007 - International Conference on Signal Processing and Multimedia Applications, Proceedings, pp.309-316
2007

Abstract

Asymmetric dual-core SoC H264/AVC Parallel programming
This paper presents an H.264/AVC decoder realization on a dual-core SoC (System-on-Chip) platform by the well-designed macroblock level software partitioning. Furthermore, optimizations of the procedures executed on each core, and data movement between two cores are captured from software and hardware techniques. The evaluation results show that a video with D1 (720×480 pixels) resolution can reach realtime decoding by the implementation, which provides a valuable experience for similar designs.

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