Redundancy Architectures and Analysis Methodologies for 3D Memories Yield Improvement

Conference paper

B.-Y. Lin and C.-W. Wu

Proc. IEEE Int. Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST)

10/2014

Abstract

Redundancy;3D;memory;yield

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Title: Redundancy Architectures and Analysis Methodologies for 3D Memories Yield Improvement
Creators - without role: B.-Y. Lin
C.-W. Wu
Identifiers: 9957772981406774
Academic Unit: College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: Traditional Chinese
Resource Type: Conference paper
Publication Details: Proc. IEEE Int. Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST)