Abstract
In an ultra high resolution H.264/AVC decoder, accessing reference frame data stored in DRAM requires huge bandwidth. The access patterns of Motion Compensation (MC) and Deblocking Filter (DF) are very different. Therefore, straightforward access and arbitration may amplify access penalty and, thus, diminish DRAM efficiency. We propose three schemes, access pattern uniformization, Macro Block (MB)-column-based mapping and task-based arbitration, to minimize the DRAM access latency including both penalty and amount of transferred data. Experimental results on a pure hardwired QFHD (3840×2160) H.264/AVC decoder system shows that by employing the proposed schemes, we achieve 86% saving in DRAM access latency. © 2008 IEEE.