摘要
In this paper, we propose two mechanisms: value-aware error-marking pattern (VA-EMP) and sequential access error correction to relieve the effect of SA faults on NVM-based accelerators. VA-EMP serves as a low-cost and effective solution. VA-EMP reserves a specific value in the exponent (EXP) field to indicate data affected by exponent SA1 faults, enabling efficient error marking with minimal hardware overhead. Sequential access error correction exploits the inherent sequential dataflow property of neural networks, which can reduce the storage and combinational circuit overhead of SA fault correction. By integrating these two schemes, accuracy is preserved while minimizing the power and area overhead associated with the combinational circuits used for SA fault marking and correction in NVM-based accelerators. The evaluation results reveal that our proposed mechanisms can help enhance the SA fault tolerance rate up to 0.2% on the Imagenet dataset within 2% accuracy loss. Overall, our proposed mechanisms can enhance the fault resilience of NVM-based accelerators with only 3.5% hardware overhead.