Abstract
Three-dimensional integrated circuits (3D-ICs) packaging has attracted a lots of attentions due to it has advantages of integrating heterogeneous functions among stacked chips. The thermal mismatch stresses with regard to interconnects composed through silicon via (TSV) and microbump induced by thermal cycling loads becomes a serious concern while a thinner stacked die thickness is required. To shrink the foregoing thickness less than 10 μm, a novel assembly approach assisted with the use of pre-stuffed molding material at the wafer-level grinding process is proposed in this research. In addition, parametric estimations of the induced stress/strain from the geometries of fine-pitch TSVs under temperature cycling loads is also performed by using a non-linear finite element analysis. As silicon chip is thick, the capability of stress released mechanism for the TSV and microbump is found to depend upon the adoption of underfill material with the proper selection of its elastic modulus. By contrast, the non-linear stress/strain at the entire interconnects of 3D-ICs package with extreme thin stacked chips reduce since the excellent flexibility provided by silicon chip is elaborated. The examined results presented in this study are valuable to the configuration designs and the feasibility of 3D-ICs package with thin stacked chips utilized the proposed assembly approach.